1. Field of the Invention
This invention relates to improvements in non-volatile dielectric memory cell devices and methods for operating such devices, and more particularly to improvements in scalable non-volatile dielectric memory cell device construction and biasing circuitry used therein, and to methods for reducing disturb conditions when reading, erasing, or programming non-volatile dielectric memory cells.
2. Relevant Background
Nonvolatile memory cells of the type in which a dielectric body is configured to exhibit an electric field between the channel and gate of a field effect transistor (FET) device are becoming of increased interest. In such memory cells, although various storage mechanisms may be provided by different known dielectric materials, generally, various physical or electrical changes may be selectively programmed into the cell dielectric which result in electric fields that control a current flow in the channel of the memory transistor when the cell is addressed. Usually, individual memory cells are programmed and erased by applying particular programming voltages, often much higher than normal operating read voltages, between the gate and the source, drain, and substrate of the cell transistors. Once the cell has been programmed, a current flow induced in the channel is measurably influenced by the field produced by the dielectric, sensed by various known sensing techniques, and interpreted as a logical one or zero.
One of the major problems prior art cells have experienced is a so-called "read disturb" condition. A "disturb" is condition that diminishes the quality of the data in the cell, or in some cases, actually changes the data held in the dielectric. Disturb conditions occur primarily when a cell is read, although disturbs can occur whenever a memory array is addressed. Read disturb effects are generally only slight for each read event on any particular cell, but, in the past, read events cumulatively operate to change the information stored in the dielectric material of the cell, resulting particularly in an erased cell appearing as if it had been programmed or a programmed cell appearing as if it had been erased. A disturb condition of this proportion renders the cell, or an array in which it is embodied, virtually useless, since the number of times any cell can be read is limited.
The effects of disturb conditions are generally more widespread in a memory array than merely the particular cells being addressed. Since memory cells in most memory array constructions share some common interconnecting lines, read voltages to read a specific addressed cell are often also applied to at least some elements of adjacent and nearby cells. These unwanted voltages also may tend to create read disturb problems on the non-addressed cells, as well.
In some applications, to address these read disturb problems, multiple transistors have been employed in each memory cell to isolate the memory transistor of the cell from unintended voltages, especially when common interconnecting lines may be employed. Typically, in multiple transistor arrangements, each memory cell has three transistors, with an isolating transistor located both above and below the memory transistor. In fact, such upper isolation transistor typically may be used to select the memory cell transistor when it is addressed in order to isolate the selection voltages from the gate of the memory cell transistor itself to minimize the possibilities of read disturb events.
Although multiple transistors are widely used for voltage isolation, recently single cell nonvolatile dielectric memory arrays have been proposed. The single memory cells are addressed in read operations by an increased voltage, on the order of twice the magnitude of a supply voltage, V.sub.cc, applied to the drain of the memory transistor, with V.sub.cc applied to the gate and source. This requires special voltage doubler or multiplier circuits on the memory array chip, and results in voltages applied to the transistor that are higher than necessary. Such techniques also are generally not scalable, since device sizes are being increasingly smaller but without concomitant supply voltage reductions. This produces significantly higher fields within the memory transistor and its memory retention dielectric.